In contrast to conventional planar metal-oxide-semiconductor field-effect transistors (“MOSFETs”), multi-gate transistors incorporate two or more gates into a single device. Relative to single gate transistors, multi-gate transistors reduce off-state current leakage, increase on-state current flow, and reduce overall power consumption. Multi-gate devices having non-planar topographies also tend to be more compact than conventional planar transistors and consequently permit higher device densities to be achieved.
One known type of non-planar, multi-gate transistor, commonly referred to as a “finFET,” includes two or more parallel fins (“fin structures”) formed on a semiconductor substrate. The fin structures extend along a first axis between common source and drain electrodes. In conventional finFET fabrication, the crystalline semiconductor material forming the fin structures is arranged such that the sidewalls of the fin structures extending in the first axis direction are parallel to the crystalline material's (110) plane, while the upper surfaces of the fin structures are parallel to the crystalline material's (100) plane.
FinFETs further include at least one conductive gate structure that is formed over the fin structures and extends along a second axis generally perpendicular to the first axis. Source and drain regions are formed in each fin structure on opposite sides of the gate structure. The gate extends across and over the fin structures such that an intermediate region of the gate conformally overlays three surfaces of each fin structure (i.e., an upper surface, a first sidewall surface, and a second opposing sidewall surface of each fin). Because the gate structure surrounds the fin structure on three surfaces, the finFET essentially has three gates controlling the current through the fin structure or channel region. These three gates provide three channels for electrical signals to travel, thus effectively increasing the conductivity per unit surface area as compared to a conventional planar transistor.
While providing the advantages noted above, finFETs and other non-planar multi-gate devices (e.g., triFETs) can be somewhat difficult to fabricate due to their unique topographies, particularly at advanced technology nodes. One particular difficulty is obtaining high PFET mobility at a scaled gate pitch because the conventional embedded SiGe volume decreases at each technology node.
It may be possible to use an epitaxial cladding layer, such as silicon germanium (SiGe) to form the channel material to provide high PFET mobility. However, while the epitaxial deposition of cladding material is easily incorporated into the processing of planar transistor structures, such a process introduces drawbacks for non-planar transistors, as conventionally their fin sidewall surfaces are in the (110) plane. Epitaxial deposition of cladding material on surfaces in the (110) plane results in the formation of faceted cladding layers with non-uniform thicknesses across the original Si fin. Non-uniformity in the thickness of diamond-shaped cladding layers provides a detrimental impact to device performance.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with improved non-planar transistor structures. Also, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with uniform cladding layers. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.